Elitegroup Computer Systems BIOS, p5txa11, Version 1.1 BIOS Driver

1. Adjust DRAM timing for Cyrix P200+ and M2 CPUs running at 75 MHz bus speed as follows:

(1) DRAM R/W leadoff: 11/7/4

(2) DRAM Read Burst Timing (FP/EDO): x333/x444

(3) DRAM write Burst Timing: X333

(4) Fast RAS to CAS Delay: 3 CLKs

(5) Fast MA to RAS# Delay: 1 CLKs

(6) SDRAM (CAS/RAS Latency): 3/3

(7) Refresh RAS# Assertion: 4

(8) Disable NA# assertion

(9) Hide "DRAM Timing" item

2. Support Cyrix M2 and AMD K6 CPUs